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RT9246
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
The RT9246 is a multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9246 controls 2 or 3 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9246 controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9246 supports K8 CPU by 5-bit VID input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system.
Features
Multi-Phase Power Conversion with Automatic Phase Selection K8 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by RDS(ON) Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number RoHS Compliant and 100% Lead (Pb)-Free
Applications
AMD(R) AthlonTM 64 and OpteronTM Processors Voltage Regulator Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
VID4 VID3 VID2 VID1 VID0 SS2 SGND FB COMP PGOOD DVD SS RT VOSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PWM1 PWM2 PWM3 ISN1 ISP1 ISP2 ISP3 ISN23 GND ADJ VDIF VSEN IMAX
Ordering Information
RT9246 Package Type C : TSSOP-28 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
2 3 4 5 6 7 8 9 10 11 12 13 14
TSSOP-28
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. DS9246-06 March 2007 www.richtek.com 1
+12V C5 1uF C6 R13 10 D1 1N4148 1 BST DRVH SW VCC 5 VIN DRVL PGND 6 IPD06N03LA C8 0.01uF Q2 R14 4.7 7 IPD09N03LA L1 1uH C7 2200uF
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+12V
RT9246
RT9603
8
Q1
4.7uF
+5V 4 C4 1uF 2
C3 1uF
RT9246
VCC PWM1 +12V +12V C10 1uF C11 R7 3k R8 3k BST DRVH SW 4 VCC 5 VIN DRVL IPD06N03LA PGND 6 C9 1uF 2 Q4 7 IPD09N03LA R9 3k 1 4.7uF R15 10 D2 1N4148 C12 2200uF PWM2 PWM3 ISN1 24 25 Q3 L2 1uH 26 27 28
VID4 >
1
VID4
Typical Application Circuit
VID3 >
2
VID3
VID2 >
3
VID2
VCORE C18 to C22 2200uF x 5
VID1 >
4
VID1
VID0 >
5
VID0
C1 0.1uF ISP1 ISP2 ISP3 ISN23 GND ADJ VDIF VSEN +12V IMAX R17 10 D3 1N4148 15 16 C14 1uF 17 +12V 18 19 20 R11 1.5k 21 R10 3k 22 23 8
RT9603
6
SS2
7
SGND
8
FB
R16 4.7 C13 0.01uF
C23 to C26 2200uF x 4
R1 15k
22nF
9
COMP
33pF
PG_VCORE <
10
PGOOD
11
R2 2.4k
DVD
+12V
C2 0.1uF
12
SS
R3 9k
13
RT
14
VOSS
C15 4.7uF 1
R4 1k R12 12k
R5 12k
C16 2200uF
R6 100k
RT9603
BST DRVH SW 4 VCC 2
Q5 8 7 IPD09N03LA Q6 5 R18 4.7 L2 1uH
C13 1uF
VIN PGND 6
DRVL IPD06N03LA
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C17 0.01uF
RT9246
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5) DAC voltage identification inputs for K8. These pins are internally pulled to 2.4V if left open. SS2 (Pin 6) DAC O/P ramping speed control for K8. Connect this pin to GND with a capacitor to set the rising/falling time at VID jump. SGND (Pin 7) VCORE differential sense negative input. FB (Pin 8) Inverting input of the internal error amplifier. COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. PGOOD (Pin 10) Power good open-drain output. DVD (Pin 11) Programmable power UVLO detection or converter enable input. SS (Pin 12) Connect this SS pin to GND with a capacitor to set the soft-start time interval.
450 400 350 300
RT (Pin 13) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. VOSS (Pin 14) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. IMAX (Pin 15) Over-Current protection set. VSEN (Pin 16) VCORE differential sense positive input. VDIF (Pin 17) VCORE differential sense output. ADJ (Pin 18) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. GND (Pin 19) IC ground. ISN23 (Pin 20) RDS(ON) current sense inputs from converter 2nd & 3rd phase channel sense components' GND node. ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21) RDS(ON) current sense inputs for individual converter channels. Tie this pin to the component's sense node. ISN1 (Pin 24) RDS(ON) current sense inputs from converter 1st channel sense component's GND node. PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 2 channels, connect PWM3 high. VCC (Pin 28)
Frequency vs. RRT
f OSC(kHz)
250 200 150 100 50 0 0 10 20 30 40 50 60 70
IC power supply. Connect this pin to a 5V supply.
RRT (k )
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OCP Setting Power On Reset ++ PWMCP
INH
Function Block Diagram
++ PWMCP
INH
OVP Trip Point ++
+ +
DAC + Droop
+
PG Trip Point
Offset Currrent Source Current Correction
+ +
VOSS
ERROR AMP GAP AMP
SGND SS Control
+ +
VSEN
BUFFER AMP
SUM/M
DS9246-06 March 2007
COMP SS
VDIF
FB
ADJ
GND
+
-
+
-
-
+
VID0 VID1 VID2 VID3 VID4 SS2
INH
DAC
Oscillator & Sawtooth
-
+
+
-
-
+
-
+
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IMAX PGOOD VCC DVD RT
INH
RT9246
PWM Logic & Driver
PWM1
PWM Logic & Driver
PWM2
PWM Logic & Driver
PWM3
PWMCP
ISN1 ISP1
ISP2 ISN23 ISP3
RT9246
Table 1. Output Voltage Program
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Output Voltage DACOUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.200 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
Note: (1) 0 : Connected to GND (2) 1 : Open
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RT9246
Absolute Maximum Ratings
(Note 1) 7V GND-0.3V to VCC+0.3V 1W 100C/W 150C 260C -65C to 150C 2kV 200V Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C TSSOP-28 -----------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) TSSOP-28, JA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range --------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID4) Input Low DAC (VID0-VID4) Input High
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Symbol
Test Conditions
Min
Typ
Max
Units
ICC
PWM 1,2,3 Open
--
12
--
mA
VCCRTH VCCHYS Input High Input Low VDVDTP VDVDHYS
VCC Rising
4.0 0.2
4.2 0.5 0.85 250
4.5 -0.91 --
V V V mV
Enable
0.79 --
fOSC fOSC_ADJ VOSC VRV
RRT = 12k
170 50
200 -1.9 1.0 66 0.60
230 400 --75 0.65
kHz kHz V V % V
RRT = 12k
--62
VRT
RRT = 12k VDAC 1V VDAC < 1V
0.55
VDAC VILDAC VIHDAC
-1 -10 -2
-----
+1 +10 0.8 --
% mV V V
To be continued
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RT9246
Parameter DAC (VID0-VID4) Pull-up Voltage DAC (VID0-VID4) Bias Current VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Differential Sense Amplifier Input Impedance Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier ISP 1,2,3 Full Scale Source Current ISP 1,2,3 Current for OCP Protection IMAX Voltage SS Current Over-Voltage Trip (VSEN/DACOUT) Power Good Lower Threshold (VSEN/DACOUT) Output Low Voltage VPGOOD- VPGOODL VSEN Rising IPGOOD = 4mA --92 --0.2 % V VIMAX ISS OVT RIMAX = 10k VSS = 1V 0.55 --0.60 13 140 0.65 --V A % IISPFSS IISPOCP 60 90 ----A A ZIMP GBW SR ---16 10 3 ---k MHz V/s GBW SR COMP = 10pF ---85 10 3 ---dB MHz V/s IBIAS_DAC VVOSS RVOSS = 100k Symbol Test Conditions Min 2.2 40 0.95 Typ 2.4 60 1.0 Max 2.6 80 1.05 Units V A V
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at T A = 25C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
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RT9246
Typical Operating Characteristics
Current Balance
ILOAD = 30A
Current Balance
ILOAD = 60A
PWM2 PWM1 PWM3 IPWM2 IPWM1 IPWM3
(5V/Div)
PWM2 PWM1 PWM3 IPWM2 IPWM1 IPWM3
(5V/Div)
(2.5A/Div)
(5A/Div)
Time (1us/Div)
Time (1us/Div)
Current Balance @ Soft Start
ILOAD = 30A (5V/Div)
Current Balance @ Soft Start
ILOAD = 0A
SS
(5A/Div)
SS
(5V/Div)
(0.5A/Div)
IPWM1 IPWM1 IPWM2 IPWM3 Time (10ms/Div) IPWM2 Time (10ms/Div) IPWM3
DVD Disable
DVD V CORE SS PGOOD
(500mV/Div) (1V/Div) (200mV/Div) (200mV/Div)
DVD Enable
V CORE DVD
(200mV/Div) (200mV/Div)
SS
(1V/Div)
PGOOD
(500mV/Div)
Time (2ms/Div)
Time (4ms/Div)
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RT9246
OCP Steady State
ILOAD = 30A to short (5V/Div)
OCP Power Up
ILOAD = short
SS
SS
(5V/Div)
(5V/Div)
(5V/Div)
PWM
PWM
(10A/Div)
(5A/Div)
IPWM3 Time (20ms/Div)
IPWM3 Time (40ms/Div)
Soft Start
VCORE (200mV/Div)
Transient Response
PWM1 PWM2
SS (1V/Div)
PWM3
V CORE
PGOOD (1V/Div)
Time (10ms/Div)
Time (200us/Div)
VID On Fly Falling
CSS2 = 0F CSS2 = 0F
VID On Fly Rising
(5V/Div)
VID V CORE SS
(500mV/Div)
VID V CORE SS
(5V/Div)
(500mV/Div) (500mV/Div)
(500mV/Div)
Time (200ns/Div)
Time (200ns/Div)
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RT9246
VID On Fly Falling
CSS2 = 1nF CSS2 = 1nF (5V/Div)
VID On Fly Rising
VID V CORE SS
(500mV/Div)
VID V CORE
(500mV/Div)
(5V/Div) (500mV/Div) (500mV/Div)
SS
Time (200ns/Div)
Time (200ns/Div)
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DS9246-06 March 2007
RT9246
Application Information
RT9246 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9246 and its companion MOSFET driver provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9246 senses the CPU VCORE by an precise instrumental amplifier to minimize the voltage drop on PCB trace at heavy load. VSEN & SGND are the differential inputs. VDIF is the output node of the differential voltage & the input for PGOOD & OVP sense. The internal high accuracy VID DAC provides the reference voltage for K8 compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9246 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Load Droop The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called "active voltage positioning" can reduce the output voltage ripple at load transient and the LC filter size. Phase Setting and Converter Start Up RT9246 interfaces with companion MOSFET drivers (like RT9600, RT9602 or RT9603 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) pins sense the interface voltage at IC POR period (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Please tie the PWM output to VCC and the current sense pins to GND or left floating if the channel is unused. For 2-Channel application, connect PWM3 high. Current Sensing Setting RT9246 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1). Be careful to choose GND sense input, ISN, of the GM amplifier for effective channel current balance.
IX1
Fault Detection The chip detects VCORE for over voltage and power good detection. The "hiccup mode" operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage.
< < <
Current Balance
IX IX Sample & Hold
GM +
IBP
Droop Tune 2IX Over-Current Detection
R ISP1 SP1 ISN1 RS RSN1 IL
IBN
IX2
< < <
Current Balance
IX IX Sample & Hold
GM +
IBP
Droop Tune 2IX Over-Current Detection Current Balance IX
R ISP2 SP2 RS IL
IBN
ISN23
IBN
RSN23
< < <
Droop Tune 2IX IX Over-Current Detection
Sample & Hold
IX3
+ GM IBP
Channel 2 & 3 GND return
ISP3 RSP3 RS IL
Figure 1. Current Sense Circuit
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RT9246
I L x RS by local feedback. RSP RSP = RSN for channel 1 & RSP = 2RSN for channel 2 & 3 (at 3 phase operation) to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, I L (S/H) x R S V O T OFF x I X (S/H) = , I L (S/H) = I L (AVG) - , R SP L 2 V IN - V O T OFF = x 5uS for fosc = 200kHz V IN The sensing circuit gets IX = Protection and SS Function For OVP, the RT9246 detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13A current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is set by the resistor RIMAX connected to IMAX pin. OCP is triggered if one channel
Low Side MOSFET Gate Signal
I X (S/H)
V IN - V O VO - x 5uS RS V IN x = I L(AVG) - 2L R SP Falling Slope = Vo/L IL
IL(AVG)
Inductor Current
IL(S/H)
PWM Signal & High Side MOSFET Gate Signal
S/H current signal IX >
Figure 2. Inductor Current and PWM Signal DAC Offset Voltage & Droop Tuning The DAC offset voltage is set by compensation network 1V R f 1 & VOSS pin external resistors by R VOSS x 4 . The S/H current signals from power channels are injected to ADJ pin to create droop voltage. VADJ = RADJx 2 IX
0 .6 V x 1 .4 . Controller forces R IMAX
PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13A current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4).
S.S VCORE 0V
The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3).
VDAC VADJ COMP Current Source IVOSS = 1V RVOSS + EA 1 IVOSS 4 FB RF1 ADJ RADJ
COUNT= 1 COUNT= 2 COUNT==33 Count = 1 Count = 2 Count
2IX1 2IX2 2IX3
>
VCORE
Figure 3. DAC Offset Voltage & Droop Tune Circuit
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-
RVOSS
+
VOSS
+
Overload Applied
ILOAD
0A
> >
T0,T1
T2 TIME
T3,T4
Figure 4.
DS9246-06 March 2007
RT9246
3-Phase Converter and Components Function Grouping
12V
VCC
BST DRVH SW
RT9603
IN SGND VSEN VDIF PWM1 VID ISP1 ISN1 VCC BST DRVH SW COMP FB ADJ Droop Setting 12V Driver Power UVLO DAC Offset Voltage Setting DVD VOSS SS, SS2 SS2 IMAX OCP Setting ISP3 VCC PWM3 GND IN BST DRVH SW ISP2 ISN23 12V PWM2 IN VCORE 12V DRVL PGND
PGOOD
RT9246
Compensation & Offset
RT9603
DRVL PGND
RT9603
DRVL PGND Current Sense Components
Design Procedure Suggestion
Voltage Loop Setting a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). c. Kelvin sense for VCORE. Current Loop Setting a. GM amplifier S/H current (current sense component RDS(ON), ISPx & ISNx pin external resistor value, keep ISPx current < 60A at full load condition for better load line linearity). b. Over-current protection trip point (IMAX pin resistor, keep ISPx current < 90A at OCP condition for precision issue).
DS9246-06 March 2007
VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (additional resistor in compensation network). c. DAC offset voltage setting (VOSS pin & compen sation network resistor). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other item.
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RT9246
Design Example
Given:
Apply for three phase converter VIN = 12V VCORE = 1.5V ILOAD (max) = 60A VDROOP = 120mV at full load OCP trip point set at 30A for each channel (S/H) RDS(ON) = 6m of low side MOSFET at 27C L = 2H COUT = 9,000F with 2m ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero : From the following formula : V IN 12V Modulator Gain = = = 4.2 (12.46dB) V RAMP 1.9V x 3 where VRAMP : ramp amplitude of sawtooth wave
1
2
Gain (dB)
Asymptotic Bode Plot of PWM Loop Gain
100 80 60 40 20 0 -20 -40 -60 10 10 100 100 1K 1000 10K 10000 100K 100000 1M 10M 1000000 10000000
Compensated EA Gain PWM Loop Gain Modulator Gain Uncompensated EA Gain
Frequency (Hz)
Figure 6. 2. Droop & DAC Offset Setting For each channel the load current is 60A / 3 = 20A and the ripple current, IL, is given as :
5us x
LC Filter Pole = 2 x LC = 1.2kHz and ESR Zero =
1 2 x ESR x COUT
= 8.8kHz
b. EA Compensation Network : Select R1 = 2.4k, R2 = 24k, C1 = 6.6nF, C2 = 33pF and use the type 2 compensation scheme shown in Figure 5.
R2
C1
R3 R1
C3
C2 COMP + DACOUT FB
> VDIF
R3,C3 are used in type 3 compensation scheme (left NC in type 2)
The load current, IL, at S/H is20 A - IL = 18.36 A . 2 Using the following formula to select the appropriate IX (MAX) for the S/H of GM amplifier : R DS(ON) x 18.36A I X (MAX) = R SP The suggested IX is in the order of 40 to 50A, select RSP = RSN = 2.4k, then IX (MAX) will be 45.9A. VDROOP = 120mV = 45.9A x 2 x 3 (phase no.) x RADJ, therefore RADJ will be 435. The RDS(ON) of MOSFET varies with temperature rise. When the low side MOSFET working at 70C and 5000ppm/C temperature coefficient of RDS(ON), the RDS(ON) at 70C is given as : 6m x {1+ (70C - 27C) x 5000ppm/C} = 7.3m. RADJ at 70C is given as : RADJ_27C x (RDS(ON)_27C / RDS(ON)_70C) = 358 3. Over-Current Protection Setting OCP trip point set at 30A for each channel, RDS(ON) x 30A 0.6V IX = = 1.4 x RSP RIMAX , RIMAX = 11.2k Take the temperature rise into account, the RIMAX at 70C will be : RIMAX_27C x (RDS(ON)_27C / RDS(ON)_70C) = 9.2k 4. Soft-Start Capacitor Selection CSS = 0.1F is the suitable value for most application.
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1.5V 1.5V x 1 - = 3.28A 2uH 12V
Figure 5. From the following formulas : 1 1 FZ = , FP = 2 x R 2 x C 1 C1 x C 2 2 x R 2 x R2 C1 + C 2 Middle Band Gain =
R1
By calculation, the FZ = 1kHz, FP = 200kHz and Middle Band Gain is 10 (i.e 20dB). The asymptotic bode plot of EA compensation and PWM loop gain is shown as Figure 6.
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RT9246
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ISN1,ISN23 should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path.
SW1
L1
VIN RIN
VOUT
COUT CIN
RL
V
L2 SW2
Figure 7. Power Stage Ripple Current Path
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RT9246
+12V CBP Next to IC +12V or +5V PWM CBOOT LO1 CIN
Kelvin Sense
VCC CBP
+5VIN
IMAX VOSS COMP VCORE
VCC IN
BST DRVH SW
Next to IC CC
RT9603
DRVL PGND
COUT RSP
RT9246
FB ISPx ISNx RSN ADJ GND VSEN
RC Locate next to FB Pin RFB
Locate near MOSFETs
For Thermal Couple
Figure 8. Layout Consideration
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RT9246
Outline Dimension
D L
E
E1
e
A A1 b
A2
Symbol A A1 A2 b D e E E1 L
Dimensions In Millimeters Min 0.850 0.050 0.800 0.178 9.601 0.650 6.300 4.293 0.450 6.500 4.496 0.762 Max 1.200 0.152 1.050 0.305 9.804
Dimensions In Inches Min 0.033 0.002 0.031 0.007 0.378 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.386
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
DS9246-06 March 2007
www.richtek.com 17

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